Among conventional non-volatile semiconductor memory devices, a non-volatile semiconductor memory device as shown in FIGS. 10 to 11 (conventional art 1) is known. The non-volatile semiconductor memory device in the conventional art 1 includes first diffusion regions 107, select gates 103, second diffusion regions (indicated by reference numeral 121 in FIG. 10), floating gates 106, and control gates 111 (refer to FIGS. 10 and 11).
The first diffusion regions 107 are extended in (below) a surface of a substrate 101, and are provided together, being separated to one another. The first diffusion regions 107 are used as local bit lines. The select gates 103 are disposed in regions between the mutually adjacent first diffusion regions 107 above the substrate 101 via an insulating film 102, and extend in the direction in which the first diffusion regions 107 extend. The second diffusion regions (indicated by reference numeral 121 in FIG. 10) are disposed on the surface of the substrate 101 below the select gates 103 outside cell regions, and extend in a direction that crosses the select gates 103 on both sides outside the cell regions. The second diffusion regions (indicated by reference numeral 121 in FIG. 10) are employed as common sources. The floating gates 106 are storage nodes, and are disposed between the first diffusion regions 107 and the select gates 103, respectively via the insulating film 102. The floating gates 106 are arranged in the form of islands as seen from a direction normal to the plane. The control gates 111 are disposed above the floating gates 106 and the select gates 103 through an insulating film 108, and are disposed together, being separated to one another. The control gates 111 extend in the direction that crosses the select gates 103. The control gates 111 are employed as word lines.
One of the first diffusion regions 107 on both sides of a select gate 103, a floating gate 106, a control gate 111, and the select gate 103 constitute a first unit cell. The other of the first diffusion regions 107 on both sides of the select gate 103, a floating gate 106, the control gate 111, and the select gate 103 constitute a second unit cell. In this non-volatile semiconductor memory device, by applying a positive voltage to the select gate 103, an inversion layer 120 is formed on the surface of the substrate 101 below the select gate 103 in the cell regions.
An operation of the non-volatile semiconductor memory device according to the conventional art 1 will be described with reference to drawings. FIG. 12 is a schematic diagram for explaining about a read operation (read operation when electrons are not stored in a floating gate) from the semiconductor memory device according to the conventional art 1. FIG. 13 is a schematic diagram for explaining about a write operation onto the semiconductor memory device according to the conventional art 1. FIG. 14 is a schematic diagram for explaining about an erase operation from the semiconductor memory device according to the conventional art 1.
Referring to FIG. 12, for a read operation, first, in a state where electrons are not stored in the floating gate 106 (or an erased state; with a low threshold voltage), by applying positive voltages to the control gate 111, select gate 103, and the second diffusion region (indicated by reference numeral 121 in FIG. 10), respectively, electrons e move from the first diffusion region 107 through a channel immediately below the floating gate 106, moves through an inversion layer 120 formed below the select gate 103, and moves to the second diffusion region (indicated by reference numeral 121). On the other hand, in a state where the electrons are stored in the floating gate 106 (or a written state; with a higher threshold voltage), even if the positive voltages are applied to the control gate 111, select gate 103, and second diffusion region (indicated by reference numeral 121 in FIG. 10), respectively, the electrons e do not flow because there is no channel below the floating gate 106 (not shown). Reading is performed by making a judgment on data (whether it has a value of 0 or 1) to see whether the electrons e flow or not.
Referring to FIG. 13, for a write operation, positive high voltages are applied to the control gate 111 and the first diffusion region 107, and a positive low voltage of an extent that causes an electric current flow of 1 μA through a memory cell is applied to the select gate 103. The electrons e thereby move from the second diffusion region (indicated by reference numeral 121 in FIG. 10) to the first diffusion region 107 via the inversion layer 120 formed below the select gate 103. On that occasion, part of the electrons e attain high energy due to an electric field at a boundary between the select gate 103 and the floating gate 106, and thus this part of the electrons e are injected into the floating gate 106 across an insulating film 105 (tunnel oxide film) disposed beneath the floating gate 106.
Referring to FIG. 14, for an erase operation, a negative high voltage is applied to the control gate 111, and a positive high voltage is applied to the substrate 101. The electrons e are thereby drawn from the floating gate 106 to the substrate 101 through the insulating film 105 (tunnel oxide film) disposed beneath the floating gate 106.
Next, an internal circuit of the non-volatile semiconductor memory device according to the conventional art 1 will be described using drawings. FIG. 15 is a circuit diagram schematically showing the internal circuit of the non-volatile semiconductor memory device according to the conventional art 1.
The non-volatile semiconductor memory device includes a main cell region 130, a reference cell region 131, a sensor amplifier 132, a main cell decoder 135, and a reference cell decoder 136.
In the main cell region 130, memory cells shown in FIG. 11 (pairs of first and second memory cells) are arranged in the form of a matrix constituted from m rows (on an X coordinate)×n columns (on a Y coordinate). The first diffusion region (indicated by reference numeral 107 in FIG. 1) in a main cell is electrically connected to the sense amplifier 132 through a main cell local bit line MLB, a main cell block selection switch 133, and a main cell global bit line MGB. The control gates (indicated by reference numeral 111 in FIG. 11) in the main cell region 130 are electrically connected to the main cell decoder 135 via corresponding word lines (data lines) W0 to W15. Incidentally, referring to FIG. 15, reference symbol SG indicates the select gate, while reference symbol CS indicates a common source corresponding to each of the second diffusion regions 121 in FIG. 10.
In the reference cell region 131, one memory cell (one pair of the first and second unit cells) shown in FIG. 11 is arranged. The first diffusion region in a reference cell (indicated by reference numeral 107 in FIG. 11) is electrically connected to the sense amplifier 132 via a reference cell block selection switch 134 and a reference cell global bit line RGB. The control gate (indicated by reference numeral 111 in FIG. 11) in the reference cell region 131 is electrically connected to the reference cell decoder 136 through a corresponding reference cell word line RW.
The sense amplifier 132 amplifies a potential difference between the memory cell global bit line MGB and the reference cell global bit line RGB. The sense amplifier 132 is provided for each main cell global bit line MGB. The main cell decoder 135 applies a voltage to one of word lines W0 to W15 specified by an address signal. The reference cell decoder 136 applies a voltage to the word line RW.
A description will be directed to a case where the address signal indicative of “14” is sent to the main cell decoder 135 and the reference cell decoder 136. When a read operation is performed, in a state where electrons are not stored in floating gates of cells surrounded by a heavy dot-dashed line (i.e. the erased state; with the low threshold voltage) in the main cell region 130, positive voltages are applied to the select gate SG, common sources CS, and word line W14, respectively, and the main cell block selection switch 133 is turned ON. Then, currents from the common sources CS are thereby input to the sense amplifier 132 via paths indicated by heavy dotted lines. On the other hand, in the reference cell region 131, regardless of whether the address signal indicates which address, positive voltages are applied to the select gate SG, common sources CS, and reference cell word line RW, respectively, and the reference cell block selection switch 134 is turned ON. Current from the common source CS is thereby input to the sense amplifier 132 via a path indicated by a heavy dotted line. In the sense amplifier 132, a potential difference between the main cell global bit line MGB and the reference cell global bit line RGB is amplified. The 0/1 judgment is thereby performed based on data output from the sense amplifier 132.
There is also provided other conventional non-volatile semiconductor memory device that includes a first column tree, a second column tree, and a differential amplifier (of conventional art 2; refer to Patent Document 1). The first column tree includes a wiring group to which information on a first memory cell is transmitted. The second column tree includes a wiring group to which information on a second memory cell is transmitted. The differential amplifier amplifies a potential difference between a potential at a data line and a potential at a reference data line. The non-volatile semiconductor memory device further includes a column switching gate. The column switching gate couples the first column tree to the data line and also couples the second column tree to the reference data line when the first memory cell is selected. When the second memory cell is selected, the column switching gate couples the second column tree to the data line and also couples the first column tree to the reference data line. According to conventional art 2, a non-volatile semiconductor memory device having strong noise immunity, in which a capacitance of a main body side can be more accurately adjusted to a capacitance of a reference side, while suppressing an increase in the area of the device, can be obtained.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2002-8386A (FIG. 1)